Technical Field
This disclosure relates to analog-to-digital converters.
Description of Related Art
High-speed (GS/s), medium resolution (˜6 bit) ADCs are in high demand for wideband electronic systems, and many of these systems utilize AC-coupled signal paths, i.e., the communication channel blocks the close-to DC frequency components to mitigate the DC offset, flicker noise impacts, and thermal asperity. For instance, wideband wireless receivers M. S. W. Chen and R. W. Brodersen, “A subsampling radio architecture for ultrawideband communications,” IEEE Trans. on Signal Processing, vol. 55, no. 10, pp. 5018,5031, October 2007; B. Afshar, Y. Wang, A. M. Niknejad, “A Robust 24 mW 60 GHz Receiver in 90 nm Standard CMOS,” ISSCC Dig. Tech. Papers, pp. 182,605, 3-7 Feb. 2008, hard-drive read channels S. Gopalaswamy, P. McEwen, “Read channel issues in perpendicular magnetic recording,” IEEE Trans. on Magn., vol. 37, no. 4, pp. 1929-1931, July 2001, and various wireline standards L. Lei, J. M. Wilson, S. E. Mick, J. Xu, L. Zhang, P. D. Franzon, “3 Gb/s AC-coupled chip-to-chip communication using a low-swing pulse receiver,” ISSCC Dig. Tech. Papers, pp. 522,614 Vol. 1, 10-10 Feb. 2005; J. Kim; I. Verbauwhede, M-C. F. Chang, “A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1331,1340, June 2005, typically require additional DC blocking and/or high pass filtering in the receiver front end.
On the other hand, scaled CMOS technology provides increasing intrinsic device speed but lower voltage headroom. This can greatly restrict analog designs that are limited by headroom reduction. To make use of the faster speed and finer time resolutions, data converter architectures that utilize time information to quantize analog signals are emerging. They have been limited to either (a) wideband but very low resolution applications because of the non-linear voltage-to-time conversion Y. M. Tousi, E. Afshari, “A Miniature 2 mW 4 bit 1.2 GS/s Delay-Line-Based ADC in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 46, no. 10, pp. 2312,2325, October 2011, or (b) high resolution but narrowband applications, mainly due to their time quantization noise shaping property J. Kim, T. -K. Jang, Y. -G. Yoon and S. Cho, “Analysis and design of voltage-controlled oscillator based analog-to-digital converter,” IEEE Trans. Circuits. Syst. I, vol. 57, no. 1, pp. 18-30, January 2010; J. Daniels, W. Dehaene, M. Steyaert, A. Wiesbauer, “A 0.02 mm2 65 nm CMOS 30 MHz BW all-digital differential VCO-based ADC with 64 dB SNDR,” VLSI Circuits (VLSIC), 2010 IEEE Symposium on, pp. 155,156, 16-18 Jun. 2010.